With reference to FIG. 1, integrated semiconductor devices such as Gallium Arsenide Field Effect Transistors (GaAs FETs), are constructed with a source region 100 and a drain region 102 connected by an N-channel layer 104 and separated by gate 106, all mounted on a GaAs substrate 108 having a metallized ground plane 109 on its back side. In operation, the gate 106 may be biased to permit a flow of electrons from source 100 to drain 102 through GaAs N-channel layer 104, which in this mode is undepleted in the region between source 100 and drain 102. The gate 106 may also be selectively biased to create a depletion region 112 in N-channel layer 104 in the vicinity of the gate 106, thus tending to separate undepleted regions 110 and 111 of N-channel layer 104 and limit the flow of electrons from source 100 through N-channel layer 104 to drain 102. When the gate is fully biased to a pinch-off voltage V.sub.po, the depletion region 112 expands to separate undepleted regions 110 and 111 and essentially cut off the flow of electrons from source 100 to drain 102. However, in this pinch-off mode, capacitances appear between gate 106 and each of the now-separated undepleted regions 110 and 111 of N-channel layer 104. In addition, the inventors have determined that a third capacitance appears directly between undepleted region 110 and undepleted region 111.
These capacitances limit the usefulness of the semiconductor device because they reduce the off-state isolation of the device, allowing microwave-frequency signals to bypass the depletion region 112. In addition, at some cutoff frequency f.sub.co, the effective impedance of these capacitances becomes equal to the resistance between source and drain when the gate-source voltage V.sub.GS =0, so that the switch off state isolation equals the switch on state resistance. At or near this frequency, the device cannot be used for switching. The cutoff frequency f.sub.co is given by: ##EQU1## where R.sub.s is the series-equivalent resistance of the "on" state undepleted N-channel layer 104, and C.sub.SD is the pinch-off state drain-source capacitance. Although f.sub.co for certain PIN diodes is 500-1000 GigaHertz, GaAs FETs typically exhibit f.sub.co values of only about 150 GigaHertz. Thus, prior art GaAs FETs are of limited use in certain microwave and radar applications. It would be desirable to produce semiconductor switches such as GaAs FETs which exhibit lower losses and have a broader operating frequency band, but such devices have not been available.
Semiconductor etching is a well-known process which is generally used to prepare regions for subsequent contact deposition. As an example, U.S. Pat. No. 4,821,093 shows a dual-channel FET formed by etching a via opening through the back side of a semiconductor wafer and later depositing source, field plate, and drain contacts in the etched region. U.S. Pat. Nos. 4,733,283 and 4,635,343 show a GaAs semiconductor device made by etching a front side GaAs layer down to an Aluminum Gallium Arsenide (AlGaAs) etching-stoppable layer, and then forming a gate contact in the etched region. An article by K. Kenefick appearing in the Journal of the Electrochemical Society 129, No. 10, p. 2380 (1982) further illustrates general concepts of semiconductor layer etching.
As far as the inventors are aware, etching has not been used to remove back side substrate material in the absence of a desire to form some new structures on the back side of the substrate, or in any case for the purpose of reducing capacitance in a semiconductor device.